Multicycle RISC V Microprocessor for Edge computing applications

Author : Penumaka Keerthana

Abstract :This paper explores the design of a multicycle RV32IM microprocessor for edge computing applications. Leveraging the modularity of the RISC-V architecture, the RV32IM processor is tailored to address the needs of low-power, high-performance devices in real-time computing scenarios. By implementing a multicycle approach, the processor splits instruction execution into stages, allowing for a more efficient use of resources compared to single-cycle designs. This approach results in reduced hardware complexity, improved clock speeds, and better power management. The paper presents the processor's design process, performance metrics, and its suitability for applications such as IoT devices, smart sensors, and low-cost edge computing platforms.

Keywords :RISC-V, RV32IM, Edge computing, Instruction set Architecture (ISA), Jump and Link (JAL), Jump and Link register (JALR).

Conference Name :National Conference on Electrical and Power Electronics (NCEPE-25)

Conference Place Indore, India

Conference Date 5th Oct 2025